For comparison purposes, FIG. 1 shows a top view of the geometry of a conventional Metal Oxide Semiconductor (MOS) structure with gate, drain, source, and body (bulk) regions. The width of the MOS channel (gate region) is B and the length of the MOS channel is G. The lengths of the source and drain regions, S and D, respectively, are based on design rules of a particular process technology to achieve certain reliability and voltage capabilities. The total area of the MOS is A×B.
The on-resistance (Ron) of the MOS depends on the width B and length G of the MOS channel. A larger width B results in a smaller Ron, and a smaller length G results in a smaller Ron. By reducing the Ron, the number of times the MOS switches within a given time period may be increased, and thus higher processing speeds, and lower energy use per switching event, may be attained.
However, in reducing the Ron, if the width B of the MOS channel increases, the area of the MOS may increase. An increased MOS area may result in chips with less computing power in the same area, or larger chips with increased manufacturing costs. Therefore, it is advantageous to reduce the Ron without also increasing the area of the MOS.
One technique to reduce the Ron consists of mirroring two basic MOS structures such that the drain regions of each structure overlap, as shown in the geometry of FIG. 2. According to this technique, the effective width B is doubled (i.e., there are two MOS channels each with a width of B), thereby decreasing the Ron, while the total area of the structure is less than double that of a single MOS structure (i.e., less than double A×B). This structure can be repeated as shown in FIG. 3 to obtain an even smaller Ron.
The present invention provides a geometry for a MOS device that obtains even further reductions in Ron of the device, ordinarily without also increasing the area of the device.